1. Field of the Invention
This invention relates to a device and method for detecting peak level. More specifically, this invention relates to a peak level detecting device and method which has application in digital communication equipment.
2. Description of the Related Art
A peak level detecting circuit is used for an automatic gain control (AGC) circuit in digital communication equipment, and an alarm circuit etc. For example, an AGC circuit compares the peak level of an output signal from a receiving amplifier with a predetermined level and also controls to maintain constant an amplitude of the output signal from the amplifier by changing the gain of the amplifier in accordance with a compared result. In a peak level detecting circuit which is used in a negative feedback control, it is necessary to decrease errors of peak level detection in order to improve a control accuracy. The errors of peak level detection include static errors due to change of temperature and supply voltage fluctuation etc. and also include dynamic errors due to the mark-space ratio of an input digital signal. The static errors may be relatively simply decreased by a compensating circuit having characteristics corresponding to the change of temperature and supply voltage fluctuation. However, the dynamic errors are difficult to compensate because of its dependence on properties of input signals.
FIG. 8 shows a peak level detecting circuit in which the errors of peak level detection, due to a change of the mark-space ratio, have been decreased. This circuit has a differential amplifier 81, a switching transistor 82, a capacitor 83 and a buffer amplifier 84. The differential amplifier 81 includes transistors Q1, Q2 and Q3 and a resistor R1. An input signal is supplied to the base of the transistor Q2. An output signal from the amplifier 81 is supplied to the base of the switching transistor 82 which is connected to the collector of the transistor Q3. The capacitor 83 holds a peak level of an output signal from the switching transistor 82 corresponding to the output signal from the amplifier 81. A potential of the capacitor 83 is fed back to the base of the transistor Q3 in the differential amplifier 81 as negative feedback.
The buffer amplifier 84 includes transistors Q5 and Q6 and a resistor R6. The potential of the capacitor 83 corresponds to the peak level of the output signal from the differential amplifier 81 and is also supplied to the base of the transistor Q5. An output signal of the circuit is obtained from a connected terminal of the emitter of the transistor Q5 and the collector of the transistor Q6 in the buffer amplifier 84. The transistors Q1 and Q6 have their respective bases connected to a constant voltages V.sub.B, and respectively form parts of the amplifier 81 and 84. These transistors are used for forming current sources and may be replaced with resistors to simplify a constitution of the circuit.
FIG. 9(a) shows waveforms of input signals in the circuit shown in FIG. 8. FIG. 9(b) shows waveforms of signals at a connecting terminal T between the switching transistor 82 and the capacitor 83. Also, FIG. 9(c) shows waveforms of output signals in the circuit shown in FIG. 8. In FIGS. 9(a), 9(b), and 9(c), waveforms shown by dashed lines correspond to signals which have two times the mark-space ratio of signals shown by continuous lines. When the input signal to the circuit becomes a high level, an output potential from the differential amplifier 81 also correspondingly increases. When the output potential becomes higher by the base-emitter voltage V.sub.BE (=0.7 V) of the switching transistor 82 than a potential of the capacitor 83, the transistor 82 turns on and conducts and the capacitor 83 is charged. The potential of the capacitor 83 rises due to the charge and is fed back to the differential amplifier 81 as negative feedback. Thus, in the collector of the transistor Q3, an amplified signal corresponding to the difference between potentials of the input signal and the capacitor 83 appears as the output signal of the differential amplifier 81. The charging of the capacitor 83 is continued until both potentials of the capacitor 83 and the input signal to the differential amplifier 81 substantially coincide.
When the input signal to the differential amplifier 81 becomes a low level, the output potential from the amplifier 81 decreases and the switching transistor 82 is cut off. Then, the capacitor 83 is discharged through the relatively high input resistances of the differential amplifier 81 and the buffer amplifier 84, and the potential of the capacitor 83 decreases gradually with time. The errors in the peak detector accumulate due to a loss of charge caused by the discharge of the capacitor 83, and due to an insufficient charge of the capacitor 83. The loss of charges is less if the discharging time becomes short and the capacitor 83 may be charged more as the charging time becomes long. Therefore, as shown in FIG. 9(c), when the mark-space ratio of the input signal is great, peak detecting errors E are inclined to decrease.
In the peak level detecting circuit shown in FIG. 8, when a gain of the differential amplifier 81 is set to be large, it may be possible to decrease the errors in charging time too much by a function of the negative feedback. However, in discharging time, the capacitor 83 may be discharged by both the input bias currents Ib3 and Ib5 of the differential amplifier 81 and the buffer amplifier 84. Thus, the loss of charges by the discharge increases in the peak level detecting circuit having the differential amplifier 81 as compared with the no feedback type circuit without the differential amplifier 81. Therefore, peak detecting errors may not be decreased too much in charging and discharging time as a whole.
When a first stage transistor of the differential amplifier 81 is replaced with a Darlington circuit, the input bias current can be decreased in the differential amplifier 81 due to decrease of the operating current. However, the Darlington circuit deteriorates the frequency characteristics of an amplifier. The differential amplifier 81 needs to be wide band in order to properly amplify the input signal. Also, it is necessary to prevent the output waveform from deteriorating due to decrease of bandwidth so that peak detecting errors will not increase in charging time.